NXP Semiconductors Network Card ISP1562 User Manual

AN10050  
Designing a Hi-Speed USB host PCI adapter using the  
ISP1562, ISP1563  
Rev. 04 — 1 November 2007  
Application note  
Document information  
Info  
Content  
Keywords  
Abstract  
isp1562; isp1563; usb; universal serial bus; host; pci adapter  
This document contains a description of the ISP1562/3 application  
schematics and the PCB design recommendations.  
 
AN10050  
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Designing a Hi-Speed USB host PCI adapter using ISP1562/63  
1. Introduction  
The ISP1562 and the ISP1563 are Hi-Speed Universal Serial Bus (USB) host controllers  
(HCs) that can be directly connected to a standard 32-bit, 33 MHz PCI bus. For the rest  
of this document, they will be known as ‘ISP1562/3’. The ISP1562/3 complies with PCI  
Local Bus Specification Rev. 2.2 and PCI Bus Power Management Interface  
Specification Rev. 1.1. No additional logic is required to implement a complete Hi-Speed  
USB host controller solution on Peripheral Component Interconnect (PCI).  
Adapter cards based on the ISP1562/3 implement three functions: function 0 and  
function 1 for OHCI1 and OHCI2, and function 2 for EHCI. According to PCI Local Bus  
Specification, each physical PCI device may incorporate one to eight separate functions  
(logical devices). Each function contains its own memory-mapped individually  
addressable configuration space of 256 bytes, containing configuration registers.  
The configuration registers of the ISP1562/3 are used by the system’s BIOS and the  
operating system to detect the presence of the respective functions, that is, Vendor ID  
(VID) and Product ID (PID), to determine the necessary resource requirements, that is,  
memory and I/O space, interrupt lines, and so on, and for specific capabilities.  
A set of on-chip ‘operational’ registers is also defined for each of the three host  
controllers implemented in the ISP1562/3. The respective host controller device driver  
interacts with these registers to implement the USB functionality and the legacy support.  
A detailed description of configuration registers and operational registers can be found in  
the ISP1562 and ISP1563 data sheets.  
The ISP1562/3 implements two internal ‘power wells’, VDD and VDDX, to benefit from the  
PCI VAUX = 3.3 V dedicated power source, which is present on the PCI connector (pin  
A14) even when PCI VCC = 3.3 V is off. This enables the ISP1562/3 PME# signal to be  
asserted and activates the wake-up logic of the motherboard, even if the rest of the  
system is powered down; for example, in S3cold system standby mode. This is applicable  
mainly to onboard (desktop) or mobile designs, but not applicable to PCI add-on cards  
because the PCI +5 V, used for VBUS, is also off during S3cold  
.
The ISP1562/3 may use PCI VAUX to power its four internal transceivers connected to the  
ISP1562/3 VDDA_AUX (analog), and also the clock circuitry, port router, root hub and Power  
Management Event (PME#) logic connected to the ISP1562/3 VCC(I/O)_AUX (digital).  
For details on implementation of the PCB design, see Section 4.  
The power management capabilities enabled by using PCI VAUX allow system designers  
to meet the governmental energy regulations that are becoming increasingly essential  
worldwide: Energy Star/USA: 30 W standby, White Swan/Europe: 5 W standby, Blue  
Angel/Europe: 5 W standby.  
This document provides a description of the application schematics and the PCB design  
recommendations.  
2. ISP1562/3 initialization  
The following sequence is required during the ISP1562/3 initialization, for correct  
functionality:  
1. Register HcRhDescriptorA = 902h. This means that bit PSM = 1b.  
2. Register HcControl = 680h. This means that bits HCFS[1:0] = 10b (operational  
mode).  
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Designing a Hi-Speed USB host PCI adapter using ISP1562/63  
3. Register HcRhStatus = 18000h. This implies that bit LPSC = 1b (port powered).  
Microsoft Windows 2000, Windows XP and Linux drivers normally use this sequence.  
The order of the steps may, however, be reversed in Windows CE default drivers so  
changes are required for normal functionality.  
3. Description of the application schematics  
The schematics (see Section 5) contain a complete implementation of the ISP1562/3 and  
allow testing of all its features in different types of design: PCI add-on card, onboard  
design in standard desktop or mobile solution.  
In the case of a standard PCI add-on card design, some simplifications to the schematics  
can be done, as described here. Some features will not be normally used in a standard  
PCI add-on card. For example: The legacy support, wake-up from S3cold (no external  
+5 V input for VBUS) and the alternative 48 MHz clock input. All these alternatives,  
however, are included in the schematics and are described in this document.  
3.1 Distribution of power sources and power management support  
As shown in the schematics (see Section 5), a simple solution by using one jumper (JP1)  
may be adopted to choose between PCI VCC = 3.3 V or PCI VAUX = 3.3 V as the main  
power source for the ISP1562/3. Power source PCI VAUX = 3.3 V is introduced in PCI  
Local Bus Specification Revision 2.2. It allows powering an add-on card and generation  
of the PME# signal, even if the system is in a deep power management state and PCI  
VCC is off. An alternative solution to using a jumper may be a simple circuit containing a  
pair of MOSFET transistors that allows to detect the presence of PCI VAUX = 3.3 V and  
automatic selection of the input voltage.  
Selection of PCI VCC = +3.3 V must be the default position of jumper JP1 in the case of a  
standard add-on card design. The other possible position of JP1 selects PCI VAUX = 3.3 V  
for complete Power Management tests, including S3cold in the case of on-motherboard or  
notebook. Note that pins 3, 77, 98 and 100 of the ISP1562, and pins 6, 12 and 95 of the  
ISP1563 are connected to the PCB VCC(I/O)_AUX power plane and pins 86 and 93 of the  
ISP1562, and pins 104, 111, 120 and 128 of the ISP1563 are connected to the PCB  
VDDA_AUX power plane. Each of these planes is separated from PCI VAUX by its own set of  
inductors and decoupling capacitors.  
Although most of the motherboards provide the PCI VAUX power source in all system  
power management modes, including S3cold, the PCI +5 V power supply is  
simultaneously interrupted with PCI VCC = +3.3 V.  
In certain standby modes (S3cold), the devices connected to USB ports will not be  
powered once the +5 V power is removed because the VBUS voltage present on USB  
connectors is normally derived from the PCI +5 V power supply. Therefore, PCI VAUX is  
not useful in the case of a standard PCI add-on card implementation for a system wake-  
up from S3cold. It is, however, a very useful feature for onboard and mobile application  
designs because it allows additional considerable power savings and also wakes up the  
system by using a USB device. The system wake-up from S3cold, generated from a USB  
device, for example, USB mouse or USB keyboard, connected to the ISP1562/3 host  
controller must be supported in system’s BIOS, hardware (a continuous +5 V must be  
supplied to VBUS) and operating system drivers.  
To be able to test the remote wake-up, especially, from those power management states  
in which the +5 V power source on PCI is not present, for example, S3cold, a special  
connector (J1) is added for an external +5 V source. Any external independent power  
© NXP B.V. 2007. All rights reserved.  
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Designing a Hi-Speed USB host PCI adapter using ISP1562/63  
supply that provides +5 V ± 5 % @ 2 A stabilized can be used. For example, a standard  
hub power supply.  
Note the distribution of pull-up resistors in the recommended schematics. For example,  
to achieve correct functionality, it is recommended that you connect the pull-up resistors  
placed on the PWEn_N and OCn_N input signals of the power switch, for example,  
MIC2026, to DVAUX NET, maintaining a good condition of these signals even when  
+3.3 V and +5 V are off. The ‘fault flag’ pins (OCn_N) of MIC2026 are open-drain and  
require the presence of pull-up resistors. A 100 nF capacitor is used on each OCn_N  
signal to prevent false fault conditions.  
CLKRUN# is implemented in the ISP1562 on pin 42 and in the ISP1563 on pin 52. This  
signal is targeted mainly for mobile system designs. CLKRUN is an I/O pin. It is used by  
the system to safely turn-off the PCI CLK for power saving, with acknowledgment from  
the ISP1562/3 according to a predefined protocol. In the case of the PCI adapter card  
design, CLKRUN# must always be LOW because it is not present in the PCI connector.  
CLKRUN# may directly be connected to GND. For details on CLKRUN# function, refer to  
PCI Mobile Design Guide Version 1.1.  
3.2 Input clock: applies only to the ISP1563  
You can use either of the following as clock input:  
A 12 MHz crystal; the default recommended solution for best ElectroMagnetic  
Interference (EMI) results.  
A 48 MHz oscillator; this may be a useful alternative, typically, in the case of on-  
motherboard design.  
Both solutions for the input clock are shown in the schematics.  
To use a 48 MHz clock as input, connect the clock signal to the ISP1563 pin 86 (XTAL1),  
pin 87 (XTAL2) can be left open, and pin 121 (SEL48M) must be pulled up as shown in  
the schematics.  
In an add-on card configuration, normally, the 12 MHz crystal is used. In such a case,  
oscillators OSC2 and R45 are not necessary. Also, pin 121 (SEL48M) must directly be  
connected to GND. Another possibility is using a 12 MHz clock as an input. In this case,  
the 12 MHz-clock signal is directly connected to the ISP1563 pin 86 (XTAL1). This is  
similar to the case in which the 48 MHz clock is used; however, the ISP1563 pin 121  
must still be connected to GND.  
3.3 Selecting the number of ports: applies only to the ISP1563  
The selection of the number of ports, 2 or 4, is done using the SEL2PORTS signal  
(ISP1563 pin 5). It must be pulled to LOW, that is, connected to GND, for normal use of  
all four ports. If SEL2PORTS is HIGH, only two ports, that is, port 1 and port 2, are  
enabled; one port from each OHCI will be used in this case for performance  
improvement. Details regarding the power consumption and possible power savings in a  
two-port configuration can be found in the ISP1563 data sheet.  
3.4 Subsystem vendor ID and subsystem device ID  
The ISP1562/3 allows loading of the Subsystem Vendor ID (VID) and the Subsystem  
Device ID (DID) for both EHCI and OHCI from an external EEPROM. Loading of these  
values in the configuration registers of the ISP1562/3 will occur only if a value of 15h is  
found in byte 7 of the EEPROM. The necessary signals, I2C-bus clock and I2C-bus data,  
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Application note  
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Designing a Hi-Speed USB host PCI adapter using ISP1562/63  
are defined on pins 96 (SCL) and 97 (SDA) of the ISP1562, and pins 122 (SCL) and 123  
(SDA) of the ISP1563, respectively. When not in use, these signals must be connected to  
ground using a pull-down resistor, typically 10 kΩ.  
3.5 Legacy support: applies only to the ISP1563  
Legacy signals, IRQ1, IRQ12, A20OUT, KBIRQ1, MUIRQ12 and SMI#, are not normally  
used on a PCI add-on card design. In this case, the MUIRQ12 and KBIRQ1 input signals  
must be connected to GND. The other signals that are mentioned in this category (that  
are outputs) can be left open.  
Details on legacy signals and a block diagram showing correct connection of these  
signals in the case of onboard design can be found in ISP1563 Eval Board User Manual  
(UM10066).  
3.6 Overcurrent protection  
The ISP1562/3 implements the digital overcurrent protection scheme.  
The recommended solution to implement an external overcurrent protection is a standard  
power switch with integrated overcurrent detection, such as:  
LM3526 and MIC2526 (2 ports), or  
LM3544 (4 ports).  
The overcurrent protection logic of the ISP1562/3 uses the following two pins for each  
USB port:  
PWEn_N: It is used to enable or disable the respective external port power switch.  
For example, MIC2526 and LM3526.  
OCn_N: It is an input on which a fault condition on the respective USB port is  
signaled to the ISP1562/3 by the external port power-switching device.  
The fault condition that is usually signaled by an external power-switching device can be  
an overcurrent or a thermal shutdown. The port power-switching integrated devices  
commonly implement a delay of 1 ms to 3 ms to prevent false OC_N reporting because  
of inrush currents, when plugging a USB device.  
Once a fault condition is received, it will be detected by the operating system and the  
respective device driver will disable the port power switch by programming the Port  
Power (PP) bit in the PORTSC register. This device driver is the OHCI driver in the case  
of an Original USB device to create the fault condition, or the EHCI driver in the case of a  
Hi-Speed USB device to create the overcurrent condition. This is according to the USB  
port allocation at the moment when the OC# signal was asserted.  
A possible alternative is to use a resettable fuse on each port. This has the advantage of  
simplicity. It, however, does not inform the operating system of the fault condition and,  
therefore, no message is generated to inform the user. The resettable fuse will continue  
to protect the port by switching ‘on or off’ as long as the overcurrent condition persists.  
A possible enhancement of this scheme is connecting VBUS to the OCn_N input of the  
ISP1562/3 to detect the OCn_N condition, the first time VBUS is cut-off a LOW level will  
appear on the OCn_N pin.  
Using only an external PMOS transistor for overcurrent protection is not possible  
because the ISP1562/3 does not implement the analog overcurrent protection (not  
measuring the current through the transistor).  
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Designing a Hi-Speed USB host PCI adapter using ISP1562/63  
4. PCB design recommendations  
Some important recommendations for a successful PCB design, applicable to both  
adapter card and motherboard design solutions, are as follows:  
Typically, a solution using four layers PCB (signal 1, GND, VCC, signal 2) is sufficient  
for proper routing, allowing you to obtain good functionality and meeting all  
compliance tests requirements. Start your design by placing the ISP1562/3 chip, the  
major components, and routing of the high-speed DP and DM traces and clock  
traces. Also, a complete ‘clean’ solution for routing the power and GND (split planes)  
must be defined before you start routing the rest of the signals.  
The trace length for all PCI signals, except the PCI clock signal, to the PCI connector  
must be limited to a maximum of 1.5 inches.  
The length of the PCI clock signal from the PCI bus connector to the ISP1562/3 must  
be 2.5 inches ± 0.1 inch in length and must be routed to only one load. It must  
usually be ‘snaked’. Ensure that all corners of this trace are rounded. Do not use 90°  
sharp corners.  
Route the high-speed USB differential pairs over continuous GND or power planes.  
Avoid crossing anti-etch areas and any breaks in the internal planes (plane splits).  
The minimum recommended distance to a plane split is 25 mils. You must also avoid  
placing a series of via holes near the DP and DM lines because these will create  
‘break areas’ in the GND plane below. This is because of the clearance imposed by  
the manufacturing process around any via holes to an internal plane.  
Try to keep the length of the DP and DM traces equal. The maximum trace length  
mismatch between high-speed USB signal pairs must not be greater than 70 mils.  
Maintain parallelism between USB differential signals, with the trace spacing needed  
to achieve 90 Ω differential impedance. To achieve the required impedance of the  
pair traces, it is recommended that you use 8 mils traces and keep the distance  
between the DP and DM traces at 8 mils. These values may vary, depending on the  
actual PCB parameters.  
Avoid corners when routing the differential pairs DP and DM. Any 90° direction  
change of traces must be accomplished with two 45° turns or by using an arc of an  
imaginary circle tangent to the DP and DM lines.  
Avoid routing the USB differential pairs near I/O connectors, signal headers, crystals,  
oscillators, magnetic devices and power connectors.  
Maintain the maximum possible distance between high-speed USB differential pairs,  
high-speed or low-speed clock, and non-periodic signals. The minimum  
recommended distances are as follows:  
20 mils between the DP and DM traces and low-speed non-periodic signal traces  
50 mils between the DP and DM traces, and clock or high-speed periodic signal  
traces  
20 mils between two pairs of the DP and DM traces  
Avoid creating stubs to connect the 15 kΩ pull-down resistors or to test points. If a  
stub is unavoidable in the design, no stub must be greater than 80 mils.  
Route all the DP and DM lines on one layer. Do not change layers (avoid using vias)  
even to avoid crossing a plane split. It is better to place a non-split plane under high-  
speed USB signals, ground layer or power layer. It is recommended that you place a  
ground layer beneath the DP and DM lines.  
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Designing a Hi-Speed USB host PCI adapter using ISP1562/63  
The maximum allowed length of the DP and DM lines for onboard solutions (or [trace  
+ cable length] for a front-panel solution) is 18 inches.  
A decoupling capacitor must be placed on VBUS as close as possible to each USB  
connector. A value of about 150 µF/10 V is recommended on each port.  
The common-mode choke used, if really necessary, on the DP and DM lines must be  
placed as close as possible to the USB connector and must have  
Zcom < 8 Ω @ 100 MHz and Zdiff < 300 Ω @ 100 MHz.  
The common-mode choke, as well as the ElectroStatic Discharge (ESD) protection  
components will be used only if necessary (in case the design does not pass EMI or  
the ESD tests) because these may affect the signaling quality. Nevertheless, it is  
recommended that you include the necessary footprints for common-mode chokes  
and ESD protection components on the PCB as safeguards. The footprints must be  
placed as close as possible to the USB connector. Special attention must be given  
when placing additional components on the DP and DM lines and routing  
recommendations must be followed.  
Both VDDA_AUX (analog) and VCC(I/O)_AUX (digital) are derived from the PCI VAUX voltage,  
found on pin A14 of the PCI connector. VCC(I/O)_AUX can directly be connected to PCI  
V
V
AUX. VDDA_AUX is separated from PCI VAUX by an inductor and each of VCC(I/O)_AUX and  
DDA_AUX uses its own decoupling capacitors.  
The design must ensure that the VDDA_AUX and VCC(I/O)_AUX power planes are isolated  
from the main PCI 3.3 V power plane. This is achieved by creating two separate  
power planes that do not come in contact with the PCI 3.3 V power plane.  
The decoupling capacitors must be placed as close as possible to the ISP1562/3. A  
good choice is the four corners of the IC because these areas will not normally be  
occupied by traces or other components, according to the ISP1562/3 pinout.  
For good EMI testing results, it is recommended that you provide a good path from  
the USB connector shell to the chassis ground. The USB connector shell must be  
connected to an isolated ground plane.  
For more information, refer to the Intel document The USB 2.0 Platform Design  
Guideline, Rev. 1.0.  
5. Schematics  
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Designing a Hi-Speed USB host PCI adapter using ISP1562/63  
ISP1562_ES1  
PCI CONNECTOR  
USB PORTS  
POWER CONTROL  
AD[31:0]  
AD[31:0]  
PCICLK  
RST#  
IDSEL  
GNT#  
PCICLK  
RST#  
IDSEL  
GNT#  
PWE1#  
PWE1#  
PWE2#  
OC1#  
OC2#  
PWE2#  
OC1#  
OC2#  
C/BE0#  
C/BE1#  
C/BE2#  
C/BE3#  
INTA#  
C/BE0#  
C/BE1#  
C/BE2#  
C/BE3#  
INTA#  
DM1  
DP1  
DM2  
DP2  
DM1  
DP1  
DM2  
DP2  
REQ#  
REQ#  
FRAME#  
FRAME#  
TRDY#  
IRDY#  
TRDY#  
IRDY#  
DEVSEL#  
STOP#  
PERR#  
SERR#  
PAR  
DEVSEL#  
STOP#  
PERR#  
SERR#  
PAR  
PME#  
PME#  
Fig 1. ISP1562 eval board schematic – top level interfaces  
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3.3 V  
JP1  
AUX  
BLM21PG221SN1  
D3 LED  
DV  
AUX  
R1  
3
2
1
DV  
+3.3 V  
AUX  
FB 1  
330 Ω  
+
DV  
AUX  
C38  
0.1 μF  
C60  
470 pF  
C59  
C28  
0.1 μF  
HEADER 3  
47 μF / 6.3 V  
All capacitors should be placed  
as close as possible to the  
corresponding ferrite bead  
C18  
C20  
0.1 μF  
C17  
0.001 μF  
C22  
0.1 μF  
0.001 μF  
Should be placed  
as close as  
possible to pin 3  
Should be placed  
as close as  
possible to pin 55  
Should be placed  
as close as  
possible to pin 98  
AV  
DV  
AUX  
AUX  
DV  
AV  
AUX  
AUX  
+3.3 V  
BLM18PG121SN1  
FB2  
+
+
C30  
4.7μF  
C24  
0.1 μF 0.1 μF  
C25  
C26  
C27  
C23  
C10  
4.7 μF  
+
C61  
4.7 μF / 6.3 V  
C29  
0.1 μF  
C19  
1 nF  
DV  
AUX  
C21  
0.1 μF  
0.1 μF  
0.1 μF 0.1 μF  
78  
87  
OC1#  
OC2#  
OC1_N  
OC2_N  
OC1#  
OC2#  
SCL  
SDA 97  
96  
70  
SCL  
SDA  
U2A  
PWE1#  
PWE2#  
79  
88  
PWE1_N  
PWE2_N  
PWE1#  
PWE2#  
8
1
2
3
4
VCC  
A0  
AD0  
AD1  
AD2  
AD3  
AD4  
AD5  
AD6  
AD7  
AD8  
AD9  
AD10  
AD[0]  
69 AD[1]  
83  
90  
DM1  
DM2  
DM1  
DM2  
DM1  
DM2  
7
6
5
68  
AD[2]  
AD[3]  
A1  
NC/WP  
SCL  
+3.3 V  
67  
66  
65  
63  
62  
59  
57  
56  
DV  
R4  
AUX  
85  
92  
DP1  
DP2  
AD[4]  
DP1  
DP2  
DP1  
DP2  
A3  
AD[5]  
C9  
AD[6]  
FB3 is optional. Can be directly tied to ground.  
R5  
4.7 kΩ  
AD[7]  
0.1 μF  
FB3  
R7  
4.7 kΩ  
GND  
SDA  
AD[8]  
81  
RREF  
AD[9]  
AT24C01A-2.7  
12 kΩ / 1 %  
AD[10]  
AD[11]  
AD[12]  
AD[13]  
AD[14]  
AD[15]  
AD[16]  
AD[17]  
AD[18]  
AD[19]  
AD[20]  
AD[21]  
AD[22]  
AD[23]  
AD[24]  
AD[25]  
AD[26]  
AD[27]  
AD[28]  
AD[29]  
AD[30]  
AD[31]  
BLM18PG121SN1  
80  
74  
GNDA  
XTAL1  
AD11 54  
53  
22 pF  
C62  
C63  
AD12  
U2  
AD13 52  
AD14 51  
AD15 50  
AD16 34  
AD17 33  
AD18 31  
AD19 30  
AD20 29  
AD21 28  
AD22 27  
AD23 26  
ISP1562ESP  
1
2
3
4
8
7
6
5
75  
XTAL2  
VCC  
A0  
OSC1  
12 MHz  
22 pF  
R2  
R6  
0 Ω  
R3  
0 Ω  
A1  
NC/WP  
SCL  
0 Ω  
99  
7
5
47  
45  
44  
42  
41  
PME#  
PME#  
PCICLK  
RST#  
PME#  
PCICLK  
RST#  
PAR  
SERR#  
PERR#  
PCICLK  
A3  
RST#  
PAR  
PAR  
SERR#  
PERR#  
SDA  
GND  
SERR#  
PERR#  
AD24  
AD25  
AD26  
22  
21  
20  
R8  
1 kΩ  
AT24C01A-2.7  
CLKRUN#  
STOP#  
39 DEVSEL#  
STOP#  
DEVSEL#  
TRDY#  
IRDY#  
STOP#  
AD27 15  
DEVSEL#  
TRDY#  
14  
13  
38  
37  
36  
24  
8
9
4
AD28  
AD29  
TRDY#  
IRDY#  
FRAME#  
IDSEL  
GNT#  
REQ#  
INTA#  
IRDY#  
AD30 12  
FRAME#  
IDSEL  
GNT#  
FRAME#  
IDSEL  
AD31  
10  
AD[31:0]  
C/BE0#  
C/BE1#  
C/BE2#  
C/BE3#  
GNT#  
C/BE0# 60  
C/BE1# 48  
C/BE2# 35  
C/BE3# 23  
C/BE#[0]  
C/BE#[1]  
C/BE#[2]  
C/BE#[3]  
REQ#  
INTA#  
REQ#  
INTA#  
AV  
+3.3 V  
AUX  
U1  
C37  
1 nF  
C49  
1 nF  
C50  
1 nF  
C36  
0.1 μF  
C51  
1 nF  
C31  
0.1 μF  
C34  
0.1 μF  
C35  
1 nF  
C33  
0.1 μF  
C32  
0.1 μF  
All capacitors should be placed as close as possible  
to the corresponding power pins.  
Fig 2. ISP1562 eval board schematic – ISP1562  
 
CON5  
B1  
B2  
B3  
B4  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
A9  
A10  
A11  
12 V  
TCK  
GND  
TDO  
+5 V  
+5 V  
INTB  
INTD  
PRSNT 1  
RESERVED  
TRST  
+12 V  
TMS  
TDI  
+5 V  
B5  
INTA#  
INTA#  
B6  
INTA#  
INTA  
INTC  
+5 V  
RESERVED  
VIO  
B7  
B8  
B9  
B10  
B11  
GND  
RESERVED  
PRSNT2  
3.3 VAUX  
RST#  
A14  
A15  
A16  
A17  
A18  
A19  
A20  
A21  
A22  
A23  
A24  
A25  
A26  
A27  
A28  
A29  
A30  
A31  
A32  
A33  
A34  
A35  
A36  
A37  
A38  
A39  
A40  
A41  
A42  
A43  
A44  
A45  
A46  
A47  
A48  
A49  
B14  
3V3_AUX  
RESERVED  
GND  
B15  
B16  
B17  
B18  
B19  
B20  
B21  
B22  
B23  
B24  
B25  
B26  
B27  
B28  
B29  
B30  
B31  
B32  
B33  
B34  
B35  
B36  
B37  
B38  
B39  
B40  
B41  
B42  
B43  
B44  
B45  
B46  
B47  
B48  
B49  
PCICLK  
REQ#  
RST#  
GNT#  
PME#  
RST  
VIO  
GNT  
GND  
PME  
AD30  
3V3  
AD28  
AD26  
GND  
AD24  
IDSEL  
3V3  
AD22  
AD20  
GND  
AD18  
AD16  
3V3  
FRAME  
GND  
TRDY  
GND  
STOP  
3V3  
PCICLK  
REQ#  
PCICLK  
REQ#  
RST#  
GNT#  
PME#  
CLK  
GNT#  
GND  
REQ  
PME#  
AD30  
VIO  
AD31  
AD29  
AD31  
AD29  
GND  
AD28  
AD26  
AD27  
AD25  
AD27  
AD25  
3V3  
AD24  
IDSEL  
C/BE3#  
C/BE3#  
AD23  
C/BE3#  
IDSEL  
C/BE3  
IDSEL  
AD23  
GND  
AD21  
AD19  
3V3  
AD17  
C/BE2  
GND  
IRDY  
3V3  
DEVSEL  
GND  
LOCK  
PERR  
3V3  
SERR  
3V3  
C/BE1  
AD14  
GND  
AD12  
AD10  
M66EN  
AD22  
AD20  
AD21  
AD19  
AD18  
AD16  
AD17  
C/BE2#  
C/BE2#  
IRDY#  
FRAME#  
TRDY#  
C/BE2#  
IRDY#  
FRAME#  
TRDY#  
IRDY#  
TRDY#  
STOP#  
DEVSEL#  
DEVSEL#  
DEVSEL#  
STOP#  
STOP#  
PERR#  
SERR#  
PERR#  
SERR#  
PERR#  
SERR#  
RESERVED  
RESERVED  
GND  
PAR  
PAR  
AD15  
PAR  
PAR  
AD15  
3V3  
AD13  
AD11  
GND  
C/BE1#  
C/BE1#  
AD14  
C/BE1#  
AD13  
AD11  
AD12  
AD10  
AD9  
AD9  
GND  
C/BE0#  
A52  
A53  
A54  
A55  
A56  
A57  
A58  
A59  
A60  
A61  
A62  
C/BE0#  
AD8  
AD7  
B52  
B53  
B54  
B55  
B56  
B57  
B58  
B59  
B60  
B61  
B62  
AD8  
AD7  
3V3  
AD5  
AD3  
GND  
AD1  
VIO  
C/BE0  
3V3  
C/BE0#  
AD6  
AD4  
AD6  
AD4  
GND  
AD2  
AD0  
VIO  
REQ64  
+5V  
+5V  
AD5  
AD3  
AD2  
AD0  
AD1  
ACK64  
+5V  
+5V  
AD[31:0]  
+5 V  
+
PCIBUS  
+
C52  
C48  
47 μF / 10 V  
47 μF / 10 V  
C14  
0.1 μF  
C54  
1 nF  
C46  
1 nF  
C53  
0.1 μF  
C64  
100 pF  
C15  
0.1 μF  
C47  
1 nF  
C16  
0.1 μF  
C58  
47 μF / 6.3 V  
C57  
47 μF / 6.3 V  
+
+
+3.3 V  
Fig 3. ISP1562 eval board schematic – PCI edge connector  
 
R20  
560 Ω  
D
VAUX  
ESD1  
3
2
1
4
5
6
D1  
LED  
R12  
R11  
10 kΩ  
10 kΩ  
U3  
IP 4220CZ6  
PWE1#  
OC1#  
4
3
1
5
6
PWE1#  
OC1#  
ENB#  
OUTB  
GND  
V
BUS  
R9  
+5V_Standby  
FLGB#  
A
+
DM1  
DP1  
2
3
C42  
0.1 μF  
C55  
220 μF / 10 V  
C43  
1 nF  
DM1  
DP1  
D−  
10 kΩ  
C39  
C41  
0.1 μF  
TT1  
+5 V  
0.1 μF  
FB8  
BLM41PG600SN1  
BUS  
C40  
D+  
C
7
8
4
5
6
GND  
0.1 μF  
R10  
IN  
OC2#  
2
1
+
FLGA#  
ENA#  
+
OC2#  
SHIELD  
R25  
15 kΩ  
R24  
15 kΩ  
C2  
47 μF / 10 V  
C3  
1 nF  
C4  
22 μF / 10 V  
FB4  
C1  
0.01 μF  
TT2  
B
SHIELD  
10 kΩ  
PWE2#  
PWE2#  
OUTA  
CON1  
USB1  
LED  
D2  
ESD2  
BLM18PG121SN1  
MIC2526  
R14  
10 kΩ  
3
2
1
R13  
10 kΩ  
4
5
6
+5 V  
R21  
560 Ω  
IP 4220CZ6  
1
D
VAUX  
V
BUS  
+
DM2  
DP2  
2
3
C45  
1 nF  
C44  
0.1 μF  
C56  
220 μF / 10 V  
D−  
DM2  
DP2  
D+  
+5 V  
4
5
6
BUS  
GND  
SHIELD  
R27  
15 kΩ  
R26  
15 kΩ  
FB5  
SHIELD  
+
C5  
C6  
100 pF  
C7  
0.1 μF  
CON2  
USB2  
BLM18PG121SN1  
47 μF / 10 V  
Optional  
J1  
FB9  
Bracket holes  
+5 V_Standby  
BLM31PG121SN1  
1
+
SW1  
SOCKET  
C13  
100 μF / 10 V  
SW2  
SOCKET  
C12  
0.1 nF  
C11  
0.1 μF  
2
3
FB10  
BLM31PG121SN1  
Fig 4. ISP1562 eval board schematic – port power control and ESD protection  
 
AN10050  
NXP Semiconductors  
Designing a Hi-Speed USB host PCI adapter using ISP1562/63  
ISP1563_ES1  
ISP1563_ES1.SCH  
PCI  
PCICONN.SCH  
POWER_SWITCH  
C/BE0#  
C/BE1#  
C/BE0#  
POWER_SWITCH.SCH  
C/BE1#  
C/BE2#  
C/BE3#  
TRDY#  
IDSEL  
PME#  
C/BE2#  
OC1#  
OC2#  
OC3#  
OC4#  
PWE1#  
PWE2#  
PWE3#  
PWE4#  
OC1#  
OC2#  
OC3#  
C/BE3#  
TRDY#  
IDSEL  
PME#  
GNT#  
OC4#  
PWE1#  
PWE2#  
PWE3#  
PWE4#  
GNT#  
RST#  
RST#  
INTA#  
INTA#  
PCICLK  
REQ#  
STOP#  
FRAME#  
DEVSEL#  
PERR#  
SERR#  
IRDY#  
PCICLK  
REQ#  
STOP#  
FRAME#  
DEVSEL#  
PERR#  
SERR#  
DM1  
DM2  
DM3  
DM4  
DP1  
DP2  
DP3  
DP4  
DM1  
DM2  
DM3  
DM4  
DP1  
DP2  
DP3  
DP4  
IRDY#  
PAR  
PAR  
AD[31:0]  
AD[31:0]  
Fig 5. ISP1563 eval board schematic – top-level interfaces  
AN10050_4  
© NXP B.V. 2007. All rights reserved.  
Application note  
Rev. 04 — 1 November 2007  
13 of 18  
 
3.3 V  
LED  
AUX  
DV  
D5  
R41  
AUX  
BLM21PG221SN1  
FB 10  
DV  
JP1  
3
2
1
AUX  
+3.3 V  
+
HEADER 3  
330 Ω  
C17  
0.1 μF  
C48  
1 nF  
C25  
C70  
470pF  
C67  
C19  
C49  
1 nF  
All capacitors should be  
placed as close as possible  
to the corresponding ferrite  
AV  
47 μF / 6.3 V  
AUX  
0.1 μF  
0.1 μF  
DV  
AUX  
BLM18PG121SN1  
Should be placed  
as close as  
possible to pin 67  
Should be placed  
as close as  
possible to pin 95  
DV  
DV  
+
FB6  
+3.3 V  
AV  
AUX  
AUX  
C26  
0.1 μF  
C50  
1 nF  
C71  
4.7 μF/ 6.3 V  
C20  
C21  
C22  
+
C68 C23  
C24  
+
4.7 μF  
C69  
DV  
AUX  
AUX  
C18  
0.1 μF  
0.1 μF  
0.1 μF  
4.7 μF 0.1 μF  
0.1 μF  
DV  
AUX  
R28  
0.1 μF  
51 kΩ  
SEL48M  
SCL  
SDA  
R29  
51 kΩ  
121  
122  
123  
R30  
51 kΩ  
SEL48M  
SCL  
SDA  
R33  
0 Ω  
93  
91  
89  
63  
AD0  
AD1  
82  
81  
80  
79  
78  
77  
75  
74  
71  
69  
68  
66  
65  
62  
61  
AMB1  
AMB2  
AMB3  
AMB4  
AMB1  
AMB2  
AD[0]  
AD[1]  
R36  
0 Ω  
R37  
0 Ω  
AD2  
AD3  
AD[2]  
AD[3]  
AD4  
+3.3 V  
U4A  
AD[4]  
94  
92  
90  
64  
AD5  
GRN1  
GRN2  
GRN3  
GRN4  
GRN1  
GRN2  
GRN3  
GRN4  
1
8
7
6
5
AD[5]  
AD6  
A0  
VCC  
NC/WP  
SCL  
AD[6]  
AD7  
AD[7]  
AD8  
2
AD[8]  
AD9  
A1  
AD[9]  
96  
105 OC2#  
112  
114 OC4#  
OC1#  
AD10  
AD11  
AD12  
AD13  
AD14  
OC1_N  
OC2_N  
OC3_N  
OC4_N  
OC1#  
AD[10]  
AD[11]  
AD[12]  
AD[13]  
AD[14]  
AD[15]  
AD[16]  
AD[17]  
AD[18]  
AD[19]  
AD[20]  
AD[21]  
AD[22]  
AD[23]  
AD[24]  
AD[25]  
AD[26]  
AD[27]  
AD[28]  
AD[29]  
AD[30]  
AD[31]  
OC2#  
OC3#  
OC4#  
3
OC3#  
A3  
DV  
AUX  
4
97  
106  
113 PWE3#  
115 PWE4#  
PWE1#  
PWE2#  
SDA  
AD15 60  
AD16 44  
AD17 43  
AD18  
AD19 40  
AD20 39  
AD21  
AD22 37  
AD23  
AD24  
AD25 31  
PWE1_N  
PWE2_N  
PWE3_N  
PWE4_N  
GND  
PWE1#  
PWE2#  
PWE3#  
PWE4#  
C27  
0.1 μF  
R26  
4.7 kΩ  
AT24C01A-2.7  
R25  
4.7 kΩ  
41  
U4  
101 DM1  
DM1  
DM2  
DM3  
DM4  
1
2
3
DM1  
DM2  
DM3  
DM4  
8
108  
DM2  
38  
A0  
A1  
A3  
VCC  
NC/WP  
SCL  
117 DM3  
125  
DM4  
R34  
0 Ω  
36  
32  
7
6
5
R46  
R35  
DP1  
103  
0 Ω  
0 Ω  
DP1  
DP2  
DP3  
DP4  
DP1  
DP2  
DP3  
DP4  
110 DP2  
119 DP3  
FB7 is optional.  
Can be directly  
tied to ground.  
30  
25  
AD26  
AD27  
ISP1563  
DP4  
127  
AD28 24  
AD29  
23  
4
R44  
12 kΩ / 1 %  
99  
AD30 22  
AD31 20  
SDA  
GND  
RREF  
GNDA  
DV  
FB7  
AUX  
not to be implemented  
98  
AT24C01A-2.7  
BLM18PG121SN1  
AD[31:0]  
R38  
+
C73  
C72  
22 pF  
86  
87  
C/BE0#  
72  
58  
45  
33  
XTAL1  
XTAL2  
48MHz  
0Ω  
OSC2  
14  
C74  
C28  
0.1 μF  
C/BE0#  
C/BE1#  
C/BE2#  
C/BE3#  
C/BE#[0]  
C/BE#[1]  
C/BE#[2]  
C/BE#[3]  
C/BE1#  
C/BE2#  
C/BE3#  
AV  
AUX  
1
7
OSC1  
12 MHz  
2.2 μF / 10 V  
R45  
8
C33  
0.1 μF  
C34  
0.1 μF  
C35  
0.1 μF  
C32  
0.1 μF  
22 pF  
33Ω  
DV  
INTA#  
REQ#  
GNT#  
IDSEL  
FRAME#  
IRDY#  
TRDY#  
14  
19  
18  
34  
46  
47  
48  
INTA#  
REQ#  
GNT#  
IDSEL  
FRAME#  
IRDY#  
TRDY#  
DEVSEL#  
STOP#  
INTA#  
AUX  
REQ#  
GNT#  
IDSEL  
3
4
IRQ1  
IRQ12  
R31  
51 kΩ  
R32  
51 kΩ  
FRAME#  
IRDY#  
TRDY#  
DEVSEL#  
IRQ1  
IRQ12  
JP2  
2
4
6
8
1
3
5
7
7
8
9
DEVSEL# 49  
STOP#  
A20OUT  
KBIRQ1  
MUIRQ12  
SMI#  
A20OUT  
KBIRQ1  
MUIRQ12  
SMI#  
51  
STOP#  
CLKRUN#  
PERR#  
SERR#  
PAR  
R42  
1 kΩ  
52  
PERR# 54  
SERR# 55  
13  
PERR#  
SERR#  
PAR  
R39  
0 Ω  
R40  
0 Ω  
HEADER 4 X 2  
PAR  
57  
R27  
4.7 kΩ  
5
SEL2PORTS  
DV  
AUX  
All capacitors should be placed as close as possible  
to the corresponding power pins.  
RST#  
PCICLK 17  
PME#  
15  
RST#  
PCICLK  
PME#  
RST#  
PCICLK  
PME#  
R43  
1kΩ  
DV  
AUX  
C36  
1
+3.3 V  
0.1 μF  
C52  
1 nF  
C53  
1 nF  
C31  
0.1 μF  
C51  
1 nF  
C29  
0.1 μF  
C30  
0.1 μF  
U3  
Should be placed as close as  
possible to pin 12  
Fig 6. ISP1563 eval board schematic – ISP1563  
 
CON5  
B1  
B2  
B3  
B4  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
A9  
A10  
A11  
12 V  
TCK  
GND  
TDO  
+5 V  
+5 V  
INTB  
INTD  
PRSNT 1  
RESERVED  
TRST  
+12 V  
TMS  
TDI  
+5 V  
B5  
INTA#  
INTA#  
B6  
INTA#  
INTA  
INTC  
+5 V  
RESERVED  
VIO  
B7  
B8  
B9  
B10  
B11  
GND  
RESERVED  
PRSNT2  
3.3 V  
AUX  
A14  
A15  
A16  
A17  
A18  
A19  
A20  
A21  
A22  
A23  
A24  
A25  
A26  
A27  
A28  
A29  
A30  
A31  
A32  
A33  
A34  
A35  
A36  
A37  
A38  
A39  
A40  
A41  
A42  
A43  
A44  
A45  
A46  
A47  
A48  
A49  
B14  
3V3_AUX  
RESERVED  
GND  
B15  
B16  
B17  
B18  
B19  
B20  
B21  
B22  
B23  
B24  
B25  
B26  
B27  
B28  
B29  
B30  
B31  
B32  
B33  
B34  
B35  
B36  
B37  
B38  
B39  
B40  
B41  
B42  
B43  
B44  
B45  
B46  
B47  
B48  
B49  
RST#  
PCICLK  
REQ#  
RST#  
GNT#  
PME#  
RST  
VIO  
GNT  
GND  
PME  
AD30  
3V3  
AD28  
AD26  
GND  
AD24  
IDSEL  
3V3  
AD22  
AD20  
GND  
AD18  
AD16  
3V3  
FRAME  
GND  
TRDY  
GND  
STOP  
3V3  
PCICLK  
REQ#  
PCICLK  
REQ#  
RST#  
GNT#  
PME#  
CLK  
GNT#  
GND  
REQ  
PME#  
AD30  
VIO  
AD31  
AD29  
AD31  
AD29  
GND  
AD28  
AD26  
AD27  
AD25  
AD27  
AD25  
3V3  
AD24  
IDSEL  
C/BE3#  
C/BE3#  
AD23  
C/BE3#  
IDSEL  
C/BE3  
IDSEL  
AD23  
GND  
AD21  
AD19  
3V3  
AD17  
C/BE2  
GND  
IRDY  
3V3  
DEVSEL  
GND  
LOCK  
PERR  
3V3  
SERR  
3V3  
C/BE1  
AD14  
GND  
AD12  
AD10  
M66EN  
AD22  
AD20  
AD21  
AD19  
AD18  
AD16  
AD17  
C/BE2#  
C/BE2#  
IRDY#  
FRAME#  
TRDY#  
FRAME#  
TRDY#  
STOP#  
C/BE2#  
IRDY#  
FRAME#  
TRDY#  
IRDY#  
DEVSEL#  
DEVSEL#  
DEVSEL#  
STOP#  
STOP#  
PERR#  
SERR#  
PERR#  
SERR#  
PERR#  
SERR#  
RESERVED  
RESERVED  
GND  
PAR  
PAR  
AD15  
PAR  
PAR  
AD15  
3V3  
AD13  
AD11  
GND  
C/BE1#  
C/BE1#  
AD14  
C/BE1#  
AD13  
AD11  
AD12  
AD10  
AD9  
AD9  
GND  
C/BE0#  
A52  
A53  
A54  
A55  
A56  
A57  
A58  
A59  
A60  
A61  
A62  
C/BE0#  
AD8  
AD7  
B52  
B53  
B54  
B55  
B56  
B57  
B58  
B59  
B60  
B61  
B62  
AD8  
AD7  
3V3  
AD5  
AD3  
GND  
AD1  
VIO  
C/BE0  
3V3  
C/BE0#  
AD6  
AD4  
AD6  
AD4  
GND  
AD2  
AD0  
VIO  
REQ64  
+5V  
+5V  
AD5  
AD3  
AD2  
AD0  
AD1  
ACK64  
+5V  
+5V  
AD[31:0]  
+5 V  
+
PCIBUS  
+
C75  
C41  
47 μF / 10 V  
47 μF / 10 V  
C14  
0.1 μF  
C77  
1 nF  
C46  
1 nF  
C76  
0.1 μF  
C63  
100 pF  
C15  
0.1 μF  
C47  
1 nF  
C16  
0.1 μF  
C65  
47 μF / 6.3 V  
C66  
47 μF / 6.3 V  
+
+
+3.3 V  
Fig 7. ISP1563 eval board schematic – PCI edge connector  
 
R13  
560 Ω  
D
VAUX  
ESD1  
3
2
1
4
5
6
D1  
LED  
R4  
R3  
10 kΩ  
10 kΩ  
U3  
IP 4220CZ6  
PWE1#  
OC1#  
4
3
1
5
6
PWE1#  
OC1#  
ENB#  
OUTB  
GND  
V
BUS  
R1  
+5V_Standby  
FLGB#  
A
+
DM1  
DP1  
2
3
C4  
0.1 μF  
C55  
220 μF / 10 V  
C43  
1 nF  
DM1  
DP1  
D−  
10 kΩ  
C1  
TT1  
+5 V  
C3  
0.1 μF  
0.1 μF  
FB1  
BLM41PG600SN1  
BUS  
C2  
D+  
C
7
8
4
5
6
GND  
0.1 μF  
R2  
IN  
OC2#  
2
1
+
FLGA#  
ENA#  
+
OC2#  
SHIELD  
C42  
1 nF  
R18  
15 kΩ  
R17  
15 kΩ  
C54  
22 μF / 10 V  
C38  
FB2  
C37  
TT2  
B
SHIELD  
10 kΩ  
PWE2#  
PWE2#  
OUTA  
0.01 μF  
47 μF / 10 V  
CON1  
USB1  
LED  
D2  
ESD2  
BLM18PG121SN1  
MIC2526  
R7  
10 kΩ  
3
2
1
R5  
10 kΩ  
4
5
6
+5 V  
R14  
560 Ω  
IP 4220CZ6  
1
D
VAUX  
V
BUS  
+
DM2  
DP2  
2
3
C44  
1 nF  
C7  
0.1 μF  
C56  
220 μF / 10 V  
D−  
DM2  
DP2  
R20  
D+  
+5 V  
BUS  
+
4
5
6
GND  
SHIELD  
R19  
15 kΩ  
FB3  
SHIELD  
+
C39  
C40  
47 μF / 10 V  
C5  
0.1 μF  
C59  
100 pF  
C6  
0.1 μF  
15 kΩ  
C60  
100 pF  
CON2  
USB2  
47 μF / 10 V  
BLM18PG121SN1  
R15  
560 Ω  
D
VAUX  
ESD3  
3
2
1
4
5
6
D3  
LED  
R8  
R6  
10 kΩ  
10 kΩ  
U2  
IP 4220CZ6  
PWE3#  
OC3#  
4
1
5
7
PWE3#  
OC3#  
ENB#  
OUTB  
IN  
V
BUS  
R9  
3
FLGB#  
+
DM3  
DP3  
2
3
C11  
0.1 μF  
C57  
220 μF / 10 V  
C61  
1 nF  
DM3  
DP3  
D−  
10 kΩ  
C8  
0.1 μF  
C10  
0.1 μF  
C9  
D+  
6
8
4
5
6
GND  
0.1 μF  
R10  
GND  
OC4#  
2
1
FLGB#  
ENA#  
OC4#  
SHIELD  
R22  
15 kΩ  
R21  
15 kΩ  
FB4  
10 kΩ  
SHIELD  
PWE4#  
PWE4#  
OUTB  
CON3  
USB3  
LED  
D4  
ESD4  
BLM18PG121SN1  
MIC2526  
R11  
10 kΩ  
3
2
1
R12  
10 kΩ  
4
5
6
R16  
560 Ω  
IP 4220CZ6  
1
V
D
VAUX  
BUS  
+
DM4  
DP4  
2
3
C62  
1 nF  
C12  
0.1 μF  
C58  
220 μF / 10 V  
D−  
DM4  
DP4  
D+  
4
5
6
GND  
SHIELD  
R24  
15 kΩ  
R23  
15 kΩ  
FB5  
SHIELD  
Optional  
J1  
FB8  
CON4  
USB2  
Bracket holes  
+5 V_Standby  
BLM18PG121SN1  
BLM31PG121SN1  
1
+
SW1  
SOCKET  
C64  
100 μF / 10 V  
SW2  
SOCKET  
C45  
0.1 nF  
C13  
0.1 μF  
2
3
FB9  
BLM31PG121SN1  
Fig 8. ISP1563 eval board schematic – port power control and ESD protection  
 
AN10050  
NXP Semiconductors  
Designing a Hi-Speed USB host PCI adapter using ISP1562/63  
6. Legal information  
Suitability for use — NXP Semiconductors products are not designed,  
authorized or warranted to be suitable for use in medical, military, aircraft,  
space or life support equipment, nor in applications where failure or  
malfunction of a NXP Semiconductors product can reasonably be expected  
to result in personal injury, death or severe property or environmental  
damage. NXP Semiconductors accepts no liability for inclusion and/or use of  
NXP Semiconductors products in such equipment or applications and  
therefore such inclusion and/or use is for the customer’s own risk.  
6.1 Definitions  
Draft — The document is a draft version only. The content is still under  
internal review and subject to formal approval, which may result in  
modifications or additions. NXP Semiconductors does not give any  
representations or warranties as to the accuracy or completeness of  
information included herein and shall have no liability for the consequences  
of use of such information.  
Applications — Applications that are described herein for any of these  
products are for illustrative purposes only. NXP Semiconductors makes no  
representation or warranty that such applications will be suitable for the  
specified use without further testing or modification.  
6.2 Disclaimers  
General — Information in this document is believed to be accurate and  
reliable. However, NXP Semiconductors does not give any representations  
or warranties, expressed or implied, as to the accuracy or completeness of  
such information and shall have no liability for the consequences of use of  
such information.  
6.3 Trademarks  
Notice: All referenced brands, product names, service names and  
trademarks are property of their respective owners.  
I2C-bus — logo is a trademark of NXP B.V.  
Right to make changes — NXP Semiconductors reserves the right to make  
changes to information published in this document, including without  
limitation specifications and product descriptions, at any time and without  
notice. This document supersedes and replaces all information supplied prior  
to the publication hereof.  
AN10050_4  
© NXP B.V. 2007. All rights reserved.  
Application note  
Rev. 04 — 1 November 2007  
 
17 of 18  
 
AN10050  
NXP Semiconductors  
Designing a Hi-Speed USB host PCI adapter using ISP1562/63  
7. Contents  
Please be aware that important notices concerning this document and the product(s)  
described herein, have been included in the section 'Legal information'.  
© NXP B.V. 2007. All rights reserved.  
For sales office addresses, email to: [email protected]  
Date of release: 1 November 2007  
Document identifier: AN10050_4  
 
 

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